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Digital ASIC Verification Engineer

Company: Synopsys
Location: Chandler
Posted on: November 8, 2018

Job Description:


Business Title
Digital ASIC Verification Engineer


08-Aug-2018

Requisition Number
18157BR

Job Description and Requirements
Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything-where devices are getting smarter, everything's connected, and everything must be secure.

Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world's most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.

Founded in 1986, $3B+ Synopsys employs 13,000+ headquartered in Mountain View, California, located globally in over 25 countries with 120+ offices throughout North America, Europe, Japan, the Pacific Rim, India and Israel.

Synopsys is committed to fostering an environment that treats people with respect, honesty and professionalism. We're also committed to partnering with the communities in which we work. Every year, Synopsys reaches out to local communities with resources and employee leadership to support education, science programs and a variety of other activities.

Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs. Join US!

Digital ASIC Verification Engineer

IP Subsystem Solution Team at Synopsys is looking for a Digital ASIC Verification Engineer. In this role you will be responsible for developing test benches and verifying integrated IP Subsystems for our customers.
https://www.synopsys.com/designware-ip/ip-subsystems.html

Must understand one or more of the following protocols USB, PCIE, SATA, DDR, Ethernet, MACsec, IPsec, HDMI, DP and MIPI. Strong experience in ASIC verification using UVM is required. Able to design test benches to verify RTL, debug simulation failures, write verification plans, and converge on coverage goals. Any implementation skills is a plus.

Requirements:

  • BS in EE/CS with 5+ years of experience. MS is preferred.
  • Knowledge of System Verilog and UVM to develop test benches for RTL simulations
  • Experience in creating test plan and constrained random tests to meet coverage
  • Experience in creating code coverage and functional coverage plans and reports
  • Knowledge of UPF based low power design verification is a plus
  • Ability to work independently and good interpersonal skills#LI-SW1

    Hiring Location
    USA - Arizona - Chandler, USA - California - Mountain View/Sunnyvale

    Hire Type
    Employee

    Job Category
    Engineering

    Country
    United States

    Keywords: Synopsys, Chandler , Digital ASIC Verification Engineer, Engineering , Chandler, Arizona

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