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Senior Digital Design Engineering

Company: Maxim Integrated Products
Location: chandler
Posted on: May 3, 2021

Job Description:

Want to make a difference and be challenged every day? Then come to Maxim Integrated and be part of a team that pushes the boundaries of what's possible.

Join our team and experience Maxim- a highly successful, $2.3 billion company with offices and manufacturing sites around the world. We develop the high-performance analog and mixed-signal electronic products that are in the latest cars, smartphones, wearables, hearables, gaming devices, robots, factories, IOT devices, the cloud, and more.

From the day we first opened our doors in 1983, we've attracted and nurtured some of the best problem solvers, creative thinkers, and innovators in the business. Every day, we're empowering design innovation and overcoming the toughest engineering challenges, enabling our customers to create the solutions that define and shape our world. And, we do this in a culture where bold thinking, teamwork, growth and community involvement are recognized and rewarded.

Job Description Summary:

Maxim is seeking a senior-level Digital/Mixed Signal Verification/Design Engineer to verify and design integrated circuits and support assigned products through the full product life cycle in the Automotive business unit located in Chandler, AZ. Emphasis will be mainly on design, though verification assignments will also be available on an as-needed basis. Project and/or personnel leadership responsibilities may be assigned to highly qualified and motivated individuals.

Job Description:

Responsibilities may include, but are not limited to:

  • Definition, Design, and Verification of interfaces, state machines, and controlling logic required to implement new products focused on an expanding Automotive Battery Management System (BMS) market
  • RTL digital architecture, design, and problem solving with a focus on accuracy, safety, and quality
  • Development and validation of Verification IP (VIP) required for UVM
  • Development of directed and constrained random test cases in SystemVerilog
  • Assist and manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity
  • AMS and real number modeling of analog blocks
  • Digital synthesis, place-and-route supervision, including STA, LEC, GLS, etc. tasks as needed by the project
  • Project leadership responsibilities
  • Possible personnel leadership/mentorship roles (for qualified candidates)

Minimum Qualifications

  • BSEE + 6 years or MSEE + 4 years Digital and/or Mixed Signal IC design/verification experience.
  • Strong written and verbal communication skills.
  • Strong RTL and general coding, object-oriented programming, and documentation skills.
  • RTL design for synchronous applications, including multiple clock domains in Silicon (asynchronous design experience also a plus).
  • Strong SystemVerilog fluency in design, simulation, and verification domains.
  • Extensive experience with a scripting language (Perl, Python, C, etc.)
  • Experience developing or collaborating on UVM test plans, environments, and test cases.
  • Demonstrated success in project & block level leadership roles.
  • Knowledge of and capability to execute the entire digital design process without significant assistance (verification experience or leadership also a plus).
  • Motivation to learn and master the full digital design and verification process (eventually covering all areas of experience listed below).

Preferred Qualifications

  • Definition and implementation of custom digital interfaces (I2C, SPI, UART, etc.)
  • Definition, design, and verification experience with custom state machines and control logic for use with analog circuits such as data converters, mixed signal processing functions, references, linear regulators, etc.
  • Advanced RTL coding skills (with style and comments supporting thorough peer review)
  • Ability to verify and debug at the block level to accelerate project development (DMS)
  • Mixed-signal simulation (Cadence AMS), interfacing with analog functions (Verilog-AMS or real number modeling experience a plus)
  • Experience with verification test plan creation, coverage closure, test case, and regression suite development (SystemVerilog/UVM a plus)
  • Logic synthesis, interfacing with place & route staff, static timing analysis, logic equivalency checking, etc.
  • Design for test, scan insertion, ATPG, functional test vectors, etc.
  • Product definition involvement
  • Technical project management
  • Mentorship and development of personnel and/or small teams
  • Experience in introducing products to the market
  • Experience supporting customer development and/or defect investigation and containment



Work Experience:

Non - Manager

Pay Rate Type:


Eligible for Relocation:


Eligible for Work Visa Sponsorship:


This position may require a deemed export control license for compliance with applicable laws and regulations; including but not limited to US Government International Traffic in Arms Regulations (ITAR), US Export Administration Regulations (EAR), or US Treasury Regulations. If required, placement is contingent on Maxim's ability to apply for and obtain an export control license on your behalf.

Maxim is proud to be an equal opportunity employer and is committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity, or protected veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you have a disability or special need that requires accommodation, please let us know.

Keywords: Maxim Integrated Products, Chandler , Senior Digital Design Engineering, Other , chandler, Arizona

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